The present invention relates generally to three dimensional (3D) integrated circuits, more particularly to 3D integrated circuits with through semiconductor vias, and methods of manufacturing the same.
To reduce manufacturing costs and improve integrated circuit performance, the semiconductor industry has experienced continuous increasing of the integration density of various electronic components or reducing the minimum feature size of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, the increasing of integrated circuit (IC) is essentially two-dimensional (2D) in nature since it is easy to manufacture. For last four decades, the scaling down of the minimum feature size of electronic devices relies on improvements in lithography technology. However, there are physical limits to both lithography technology and the minimum device size. In addition, when the number of devices in an IC increases, the length of interconnections among devices increase dramatically. In this case, it is difficult to meet the requirements for bandwidth, resistance-capacitance (RC) delay and power consumption.
The limitations and difficulties mentioned-above can be solved by introducing three-dimensional (3D) integrated circuits. 3D integration provides significant benefits in terms of transistor density and wire reduction. A typical 3D integration process is bonding two 2D IC chips together with chip-to-chip or chip-to-wafer or wafer-to-wafer bonding. Typical interconnections between the ICs in the two 2D IC chips are so-called through-semiconductor-vias, which go through at least one of the two 2D IC chips.
Since multiple chips can be stacked together to form a 3D IC, the integration density of devices in the 3D IC is much higher than 2D ICs and the interconnect length in the 3D IC is much shorter than 2D ICs. In addition, before 2D IC chips are bonded together, they can be tested to check if they are in good conditions or satisfy 3D integration requirements. To improve yields of 3D ICs, the 2D IC chips that meet 3D integration requirements are selected to bond together. Therefore, 3D ICs can be used to reduce IC manufacturing costs, increase IC performance and improve chip yields. It is also the potential to be the next generation of mainstream IC technology.
Various 3D integrated circuits have been proposed by Rahman et al U.S. Pat. No. 7,518,398, Leung et al U.S. Patent Application Publication US2009/0294974, Andry et al U.S. Patent Application Publication US2010/0032764, Shi et al U.S. Patent Application Publication US2009/0243046, Puttaswamy et al, “Implementing Caches in a 3D Technology for High Performance Processors,” ICCD, pp. 525-532, 2005 International Conference on Computer Design (2005), and Burns et al., “A Wafer-Scale 3-D Circuit Integration Technology”, IEEE Transactions on Electron Devices, 53, No. 10 (2006), pp 2507-2516, the disclosures of which are incorporated by reference herein.
Of the foregoing references, Rahman et al U.S. Pat. No. 7,518,398 discloses forming through via connections between two ICs. Leung et al U.S. Patent Application Publication US2009/0294974 discloses a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. Andry et al U.S. Patent Application Publication US2010/0032764 discloses a structure of conductive through-silicon-vias that are formed by using dummy poly-silicon vias. Shi et al U.S. Patent Application Publication US2009/0243046 discloses a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. Puttaswamy et al paper discussed the benefits of 3D integrated circuit, and Burns et al paper disclose the formation of through vias that connect two levels of metal wherein the vias are formed through the silicon after the wafers are bonded.
A 3D integrated circuit usually is formed by bonding two or more patterned wafers together to make electrical contacts among the ICs in different wafers. It is difficult to obtain high quality bonding interfaces and good electrical contacts with patterned wafers due to non-uniformity and heterogeneity in the bonding interfaces. There exists a need for a 3D semiconductor structure in which un-uniformity and heterogeneity of bonding interfaces does not adversely impact electrical contacts that are formed by bonding two wafers or chips.